Ziyi (Roy) Zhao — Firmware Design Developer

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Skills

SOFTWARE BUS

C/C++UEFIBash PythonSwiftJava HTMLCSS

HARDWARE / INTERFACE BUS

PCIeI²C / I3CGPIO QSGMIIx86 (Intel/AMD)ARM Bluetooth

TOOLING BUS

GitSVNMercurial Linux KernelOscilloscopeWireshark

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Firmware Design Developer — Fortinet

Jan 2020 – Present
Burnaby, BC

Develop and maintain UEFI/BIOS firmware for multiple FortiGate platforms across x86 and ARM, integrating custom and third-party components via PCIe, I²C, and QSGMII while ensuring platform stability across diverse hardware configs.
Design and implement BIOS-level security and recovery mechanisms — including corruption detection, automated recovery, and multi-level tamper validation — integrated with the DevOps release pipeline for consistent, automated rollout.
Debug and resolve firmware issues by tuning chipset and interface settings in collaboration with Intel/AMD/Insyde (e.g., enabling chipset features, PCIe link training, GPIO assignments) to improve reliability and performance.
Evaluate chipset variants on vendor Customer Reference Boards; perform stress and stability testing, analyze results, and deliver reports that inform part selection and platform design decisions.
Build internal test tools and Linux-based OS images to accelerate validation and regression.

Firmware Developer (Co-op) — Avigilon (Motorola Solutions)

Sep 2018 – Apr 2019
Vancouver, BC

Improved device performance and stability by resolving embedded Linux Zeroconf IP conflict and video frame-rate issues.
Modernized code to C++11/14, replacing third-party libs with STL; reduced linked objects by ~10% in clean builds.
Updated web UI for PTZ configuration (HTML/CSS) using existing APIs; integrated with on-device C++ server.

Firmware Developer (Co-op) — Netgear Canada

Jan 2017 – Aug 2017
Richmond, BC

Implemented a temperature-sensing subsystem in C++ on a manufacturing prototype and integrated it into the final product.
Developed Android and iOS applications for internal testing in Java and Swift, and communicated with the prototype using Bluetooth LE and MQTT.

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BIOS — Corruption Recovery (Platform Firmware Resilience)

Jan 2026 – Jun 2026

PLATFORM: ALL G-SERIES PLATFORMS

Designed and implemented a BIOS-level recovery mechanism that detects firmware corruption and automatically restores affected platforms to a known-good image, deployed across all G-series product lines.
Incorporated multi-level security validation into the recovery path to guard against tampering and unauthorized firmware modification.
Integrated the recovery flow with the DevOps pipeline and release process, enabling automated validation and consistent rollout across builds.

BIOS — FortiGate 3000G/3500G series

Aug 2024 – Sep 2025

PLATFORM: AMD GENOA CHIPSET

Contributed to the transition of the FG3000G/FG3500G BIOS architecture from a peripheral-driven internal structure to a standards-compliant UEFI framework built on the AMD Genoa chipset.
Participated in design validation for PCIe and I²C interfaces to ensure reliable peripheral communication across the restructured architecture.
Designed and executed performance and stability validation to confirm platform readiness ahead of production release.

BIOS — FortiGate Rugged 50G/70G series

Nov 2023 – Apr 2024

PLATFORM: FORTINET ARM SoC

Developed BIOS for Fortinet ARM SoC. Collaborated with hardware and OS teams to configure GPIO and I²C interfaces across multiple prototype platforms.
Developed QA test parameters and validated hardware/software stability, releasing firmware updates to ensure RF and regulatory compliance across customer use cases.

BIOS — FortiGate 1000F/600F series

Nov 2022 – Jun 2023

PLATFORM: INTEL TATLOW CHIPSET

Developed and customized BIOS for FG600F and FG1000F based on the Intel Tatlow chipset. Adapted vendor reference code and investigated issues using Customer Reference Boards.
Integrated peripheral components via PCIe and I²C interfaces, tuning BIOS parameters and interface configurations with vendor support to ensure long-term stability under stress (≥99.9% boot success rate).

BIOS — FortiGate 3000F/3500F series

May 2020 – Aug 2021

PLATFORM: AMD ROME CHIPSET

Performed validation and stress test using the AMD Rome chipset and Customer Reference Board. Compared performance across processor SKUs within the product line.
Assisted in developing and customizing BIOS for FG3000F and FG3500F platforms, designing and executing functional and stability tests to ensure long-term performance.

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Simon Fraser University — B.A.Sc., Computer Engineering

Sep 2013 – Dec 2019
Canada